ms_top Project Status (11/19/2016 - 23:49:25)
Project File: minesweeper.xise Parser Errors: No Errors
Module Name: ms_top Implementation State: Programming File Generated
Target Device: xc6slx16-3csg324
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 1,724 18,224 9%  
    Number used as Flip Flops 1,724      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 6,054 9,112 66%  
    Number used as logic 6,030 9,112 66%  
        Number using O6 output only 4,845      
        Number using O5 output only 91      
        Number using O5 and O6 1,094      
        Number used as ROM 0      
    Number used as Memory 0 2,176 0%  
    Number used exclusively as route-thrus 24      
        Number with same-slice register load 0      
        Number with same-slice carry load 24      
        Number with other load 0      
Number of occupied Slices 2,056 2,278 90%  
Number of MUXCYs used 532 4,556 11%  
Number of LUT Flip Flop pairs used 6,097      
    Number with an unused Flip Flop 4,559 6,097 74%  
    Number with an unused LUT 43 6,097 1%  
    Number of fully used LUT-FF pairs 1,495 6,097 24%  
    Number of unique control sets 31      
    Number of slice register sites lost
        to control set restrictions
172 18,224 1%  
Number of bonded IOBs 26 232 11%  
    Number of LOCed IOBs 26 26 100%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 3 16 18%  
    Number used as BUFGs 3      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 248 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 248 0%  
Number of OLOGIC2/OSERDES2s 0 248 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 16 32 50%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 4.41      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat Nov 19 23:40:34 2016   
Translation ReportCurrentSat Nov 19 23:42:00 2016000
Map ReportCurrentSat Nov 19 23:46:16 2016   
Place and Route ReportCurrentSat Nov 19 23:47:42 2016000
Power Report     
Post-PAR Static Timing ReportCurrentSat Nov 19 23:47:59 2016003 Infos (0 new)
Bitgen ReportCurrentSat Nov 19 23:49:15 2016000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateWed Nov 16 20:54:03 2016
WebTalk ReportCurrentSat Nov 19 23:49:18 2016
WebTalk Log FileCurrentSat Nov 19 23:49:23 2016

Date Generated: 11/19/2016 - 23:49:25